Step-Down, or Buck DC/DC converters that employ a peak-current control architecture are widely used to step from a higher input voltage level to a lower output voltage level while maintaining very high efficiency. This control scheme uses an error amplifier to amplify the difference between the output voltage and a reference voltage. The resulting error voltage is then used to adjust the peak current in a power switch, thereby controlling the current delivered to the load and the resulting output voltage. Typically, such converters also make use of a compensating ramp to ensure stability. Under normal operating conditions, the output voltage is regulated so as to be essentially constant as the load current is varied. However, when the load current increases to a given design limit, it is desirable to allow the output voltage to decrease so as to maintain a constant output current. This is important to avoid damage either to the load or to the converter itself. A constant output current behavior is also important, for example, when a DC/DC converter is used to supply voltage to a large bank of capacitors. During start-up into such a load, the capacitors will initially appear as a short circuit. In order to ensure a smooth and reliable start-up, the output current must be quickly and accurately limited to a constant level. This constant output current will charge the capacitors until the voltage reaches the desired output regulation level, at which point the output current will decrease and the output voltage will settle at the regulation level.
There are, however, three significant obstacles to achieving a constant average output current characteristic during current limit. The first is the variation in the peak current limit with duty cycle due the compensating ramp.
Variation in Peak Current Limit with Duty Cycle
FIG. 1 shows a block diagram of a typical DC/DC converter using a peak-current control scheme. The converter includes a feedback arrangement including an error amplifier U3 that provides an error signal VERR1 as a function of the difference between the output voltage VOUT and a reference voltage VREF. The VERR1 signal is applied to the summer Σ. Summer Σ generates an error signal VERR2 representative of the difference between the VERR1 signal less a compensating ramp signal VRAMP. Using a comparator U1, VERR2 is compared to a voltage representing the current flowing through inductor L1 sensed by current sensor T1. The output of comparator U1 provides an input to the reset (R) input of a latch U2. The latch U2 receives a clocking input VCK at the set input (S). The Q output of the latch controls the opening and closing of the switch S1. The compensating ramp VRAMP is generated using a clocking signal VCK to open and close a switch which in turn is connected in parallel with a capacitor that receives current from a current source. VRAMP is subtracted from the error signal VERR1 so as to aid in stabilizing the current loop formed by comparator U1, latch U2, power switch S1 and current sensor T1. A clamp formed by diode D2 and voltage source VCL clamps the value of VERR1 to a maximum limited value.
Operation is as follows. At the rising edge of the clock signal VCK, latch U2 is set and switch S1 turns on. The input voltage VIN is applied to the inductor L1, and the current ramps upward. When the current sensed by T1 reaches a value equal to the error signal VERR2, the latch is reset and the switch S1 is turned off. In normal operation, the error amp U3 adjusts the value of the error signal VERR1 in order to maintain a constant output voltage. During current limit operation, however, the error signal increases until it is limited to a maximum value set by the clamp formed from diode D2 and source VCL.
Since the compensating ramp VRAMP is subtracted from the clamped error signal VERR1 to create the compensated error signal VERR2, the value of VERR2 at the moment that switch S1 is turned off will vary with the ON-time (Duty Cycle) of switch S1. As a result, the peak current during current limit will vary with output voltage, increasing as the output voltage decreases. If the amplitude of the compensating ramp is approximately equal to the clamp voltage set by VCL, then the peak current during current limit operation can vary by as much as 2:1 as the output voltage varies. This variation in the peak current is illustrated in FIG. 2.
Variation in Ripple Current
A second obstacle to obtaining a constant average current during current limit is the variation in ripple current that naturally occurs with changes in Vin and Vout. The ripple current is given approximately by:(VIN−VOUT)*tON/L, 
wherein L is the value of the inductor, and tON is the ON-time of the switch S1.
When the ripple current is very small, the average output current is nearly the same as the peak current. When the ripple current is larger, the average output current is much less than the peak current. Since it is the peak current that is actually limited, the average output current will increase as the output voltage decreases, due to the decreasing ON-time of the switch S1. This so-called peak to average error is an artifact of peak-current control, and is present even when no compensating ramp is used. FIG. 3 illustrates how the average output current changes during current limit as a result of this peak to average error. Note that for FIG. 3 the compensating ramp has been set to zero so as to better illustrate the peak to average error.
Minimum Controllable ON-Time
A third obstacle to achieving a constant average current during current limit is the minimum controllable ON-time of switch S1. In FIG. 1, this is represented by the pulse width of VCK. Since latch U2 is set dominant, switch S1 will always be on for at least this minimum on-time, TON,LIM. In current limit operation, as the output voltage is decreased, the ON-time will decrease until it reaches this limiting value TON,LIM. At this point, since the ON-time cannot be reduced any further, the average voltage delivered to the load becomes fixed, and the output current will increase significantly as the load resistance is further decreased. When the output voltage reaches zero, the average output current will be given approximately by:IAVG,MAX=VIN*TON,LIM*FSW/RPAR 
wherein Fsw is the switching frequency of switch S1, and Rpar is the parasitic resistance, which includes the switch S1, inductor and all other parasitic resistances.
FIG. 4 shows a typical voltage versus current characteristic for the DC/DC converter of FIG. 1. The initial tail-out of the average output current (the part of the curve between A and B) is caused by the variation in peak current due to slope compensation and the peak to average error. The sharp tail-out at lower output voltage (commencing at B) is caused by the minimum ON-time constraint.
The overall effect of these three obstacles is a very undesirable increase in output current during current limit operation. What is desirable is to provide a DC/DC converter that will provide a constant average output current characteristic during current limit, labeled “Desired Current Limit” in FIG. 4, a condition sometimes referred to as a “brick wall,” because of the substantial vertical fall off.